High frequency analog-to-digital converter

ABSTRACT

An analog-to-digital converter having a signal generator providing a sinusoidal reference signal which is to be compared to a high frequency analog signal, a plurality of threshold units each biased to trigger an output signal at a predetermined discrete level of the difference between the reference signal and the analog signal, a memory reset unit receiving the reference signal and providing a reset signal for clearing the output signals therefrom at a predetermined time in each cycle of the reference signal, and an encoder receiving the output signals of the threshold units and converting them into a digital code. The time of the reset signal is determined to be after either positive or negative peak of the reference signal.

United States Patent Fineran et al.

[ 1 HIGH FREQUENCY ANALOG-TO- 3,305,854 Witt ..340/347 2/1967 I DIGITALCONVERTER 3,396,381 8/1968 Aitken ..340/347 [72] Inventors: Dennis E.Finer, Santa Ana; 3,142,056 7/1964 Martin et a1. ..340/347 Samuel JFendley Mountain View 3,422,226 l/l969 Acs ..l79/15 BA a y I both ofCahf' iv Primary Examiner-Maynard R. Wilbur [73] Assignee: The UnitedStates of America as Assistant Examiner-D60 Boudl'eau represented by thSecretary f th Attorney-R. S. Sciascia and Henry Hansen Navy TR T [22]Filed: Oct. 28, 1970 [57] ABS C An analog-to-digital converter having asignal genera- [21 Appl' 84684 tor providing a sinusoidal referencesignal which is to be compared to a high frequency analog signal, a plu-52 340/347 79/ 5 AP, 7 5 BA, rality of threshold units each biased totrigger an out- 307/ 235 R, 325/38 A, 328/146, 340/347 SH Put signal ata predetermined discrete level of the dif- [51] Int. Cl .5 ..H03k 13/02ference between'the reference Signal and the analog [58] Field of SearchQ. ..340/347- signal a memmy reset receiving the reference 179/1 SA 155515 A 15 AP signal and providing a reset signal for clearing the out- A.put signals therefrom at a predetermined time in each 5 53 cycle of thereference signal, and an encoder receiving 1 r the output signals of thethreshold units and converting them into a digital code. The time of thereset [56] References signal is determined to be after either positiveor nega- UNITED STATES PATENTS tive peak of the reference signal.

3,237,113 2/1966 Klein -.33 0/69 X 4 Claims, 4 Drawing Figures SAMPLINGREFERENCE GENERATOR MEMORY B RESET g GI THRESHOLD UNIT RESHOLD u/v/rs ru-711, ENCODER THRESHOLD UNIT MENU-100012 Tm 3.701. 144

SHEET 1 UF 2 SAMPLING 1 REFERENCE GENERATOR I MEMORY 3 B RESET GI V T 25u c; THRESHOLD 7 UNIT BA|' v I 23 I 1 I THRESHOLD u/v/rs' ru -ru ENCODERi i m D THRESHOLD UNIT FIG.I

FIG. 2

MEMORY R585 7 INVENTO'R,

F G 3 v DENNlS E. FINERAN SAMUEL J. FENDLEY BY ATTORNEY mimtnumme v3.101.144

' T SHEET .2 0F 2 PRIOR ART 4 AMPLITUDE INVENTOR.

4 DENNIS E. FINERAN I SAMUEL J. FENDLEY L m km ATTORNEY 1 HIGH FREQUENCYANALOG-TO-DIGITAL H I -I CONVERTE R STATEMENT OF GOVERNMENT INTEREST,

The invention described herein may be manufacturedand used by or for theGovernment of the United States of America for governmental purposeswithout the payment of any royalties thereon or therefor.

BACKGROUND OF THE INVENTION The present invention relates to analog-todigital converters, and more particularly to improvements in apparatusfor obtaining discrete sampling of high frequency analog signals. g

In many conventional A to D (analog-to-digital) converters areferencepulse of known amplitude and duration is periodically generated againstwhich discrete samples of ananalogsignal to be converted is compared.The duration of the reference pulse determines the aperture or samplingtime as referred to herein. The aperture time is usually-a major sourceof error due to its uncertainty and more particularly due to the analogsignal amplitude'changing during the sampling time. In mostlow-frequency converters, the arnplitud'e'changes of the analog signalare usually insignificant or'tolerable over the narrow aperture timesattainable 'for'conventional techniques; but at high frequencies thegeneration and distribution of subnanosecond aperture times required tominimize the error have presented serious circuit design and packagingproblems because ofthe gigahertz bandwidths required.

SUMMARY OF THE INVENTION Accordingly, it is a general purpose and objectof the invention to provide ,a. novel and improved high frequency A to Dconverter having a relatively simple and inexpensive circuit and elementconfiguration without any trade-off in high accuracy performance.

Briefly these and other. objects are accomplished according totheinvention by generatinga sine wave sampling reference signal havingafrequency above the bandwidth: of the analog signal and an amplitudegreater than theanalog signal. The difference between the analog signaland the reference signal feeds across an array of parallel thresholdunits, each threshold unit being consecutively biased to'trigger anoutput signal at a signal difference one increment higher than thepreceding unit. Thus the signal difference is converted into discretesets of output signals which are converted into a'binary coded messageby an encoder. Each output signal is irreversible within one messagecycle, consequently the maximum signal difference occurs near the peakof the reference signal.

BRIEF DESCRIPTION OF THE DRAWINGS signals as applied to theinventiveconverter and a prior art converter.

DESCRIPIIONOF THE PREFERRED v EMBODIMENT Referring tothe inventiveembodiment of FIG. 1, an analog signal A which is to be converted is fedthrough fourteen parallel buffer amplifiers 11 to one input ofrespective threshold units 13. A reference signal generator 12, of aconventional type, provides a sinusoidal output signal B to anotherinput of respective threshold units 13 and to the input of a memoryresetj14. Signal B must be of a frequency greater than the highestanticipated frequency of signal 'A. Except as noted herein, thresholdunits 13 are identical and will be described by reference to'FIG. 2wherein signals A and B are respectively connected to one e'ndofresistors l5 and 16 which are connected in common at their other ends tothecathode of a tunnel'diode 11 and one end of a bias resistor 18. Theanode of diode 17 is connected to ground and the otherend of resistor 18is connected toa dc. power supply E- l-. Resistors I5 and 16 incombination with generator l2'must be selected to ensure that the peakcurrent amplitude through resistor 16 is greater than the maximum peakanticipated current amplitude through resistor 15. Resistor 18 isselected for each threshold unit 13 for biasing currents therethrough tocause diode 17- to switch toa high voltage state at discrete incrementsof current differences through resistors '15 and 16 thereby producing aswitching signal.

Referring now to FIG. 3,the reference signal Bis fed to one end of aresistor 29 of memory reset 14, the other end being connected in commonwith the cathode of a tunnel diode 28 and one end of a biasing resistor30. The other end of'resistor30 and the anode of diodev 28 are connectedrespectively to a dc. power supply F+ andfto ground. The junct'ion ofresistors 29 and 30 provides a reset signal C. Resistor 30 is selectedfor a biasing current therethrough to' cause diode 28 to switch to ahigh voltage state at a predetermined cur-v rent through resistor 29 sothat the off-time of signal C straddles the peak region of allanticipated frequencies of the difference between signal B and A.Signal'C is connected through, series connected resistors 22 and 20(FIG. 2) to the anode of a diode 19, the cathode thereof being connectedto the junction of resistors 15, 16 and 18. The cathode of a tunneldiode 21 is'connected to the junction of resistors 20 and 22,- and itsanodeis connected to ground. Diodes '19 and 21 function asabistableswitch passing" the forward side of the switching signal andblock-ingthereturn side.

Diodes 21 attheir cathodesprovide output signalsG' through G for therespective threshold units 13' .indicating whether, at any time within'a reset cycle generated by signal C, the condition necessary to switchdiode 17 was met. Accordingly, the combinedoutput of the'arrayofthreshold units 13is accumulative within each reset cycle such that amaximum signal difference between signal A and signal B is registered onrespective diodes 21 within each reset cycle. The output signals G to Gof respective threshold-units 13 are, in turn, connected to respectivebuffer amplifiers 25. Amplifiers 2 5 generate input signals to anencoder 23 which are converted into a coded s'i'gn'al Dior-transmission.

. 3 Operation of the invention will now be summarized with reference toFIG. 4. A signal A represents a typical maximum amplitude and bandwidthanalog signal to be converted. It is combined with a sampling referencesignal B, the difference being signal B-A at the common connections ofresistors 15 and 16. From time t to t,, memory reset 14 produces signalC at the cathode of diode 21- which blocks all outputs from the.threshold units 13. As the amplitude of signal B-A increases from t, tot threshold units 13 sequentially produce output signals G through G andremain on until cleared by signal C at 12,. Signals 6 -6 are thereforeindicative of the maximum amplitude of signal B-A within one cycle ofreset signal C and are converted by encoder 23 to binary coded signal D.1 I

n The maximum value of signal B-A will periodically occur at a time whentheslope a/b of signal B is equal to the slope a/b of signalAfSpecifically the maxima in signal B-A- occur at times t and t, whichrespectively lead and lag the peaks in signal B at and t Signal A isshown-with its maximum slopes occurring proximate the peaks of signalsB, thus'times t and indicate the largest increment of lead and'lagrespectively. A signal P is shown depicting a typical, prior artrectangular pulse sampling reference of an aperture coincident with tand r, at the forward and return sides respectively. Accordingly theeffective aperture of the inventive converter is shown to be equal tothe aperture of a prior art rectangular pulse sampling converter wherethe prior art sampling signal requires a significantly higher and widerbandwidth for its reproduction.

' Thus, the invention provides by combining a commonly available sinewave generator with a plurality of threshold units 13, made up ofcommonly available tunnel diodes l7 and 21, and buffered by typicalbuffer amplifiers 11 and 25, a sampling device whichis comparable orbetter in accuracy than the prior art rectangular pulse samplingmethods. This reduction in bandwidth is of particular value inapplications where the input signal frequency domain is in the gigahertzregion. The sampling device output produced is referenced to the peaksof the sinusoidal signal B thus providing for discrete sampling of ananalog signal A at a known time and with respect to a known signalamplitude.

Some of the many advantages and improvements over the prior art shouldnow be readily apparent. The above-described system provides significantimprovements over the prior art by allowing a much narrower bandwidthand also a much lower bandwidth to serve the same function and at thesame accuracy than that of a pulse reference system. It is particularlysignificant in a high frequency domain since at that frequency anyextensions of bandwidth are critical. Aperture time is no longersignificant since the reference signal now more closely approximates atriangular reference which by its shape alone precludes the necessity ofa tight aperturel Also, if it is found that errors due to peak flatnessare undesirable, accuracy can be improved by simply increasing theamplitude of the sine wave reference signal. This is. not possible witha rectangular pulse. I

. Obviously, many modifications and variations of the present inventionare possible in the light of the above teachings. It is therefore to beunderstood that in the scope of the appended claims the invention may bepracticed otherwise than as specifically described.

What is claimed is: 1. A high frequency analog-to-digital converter foran analog signal comprising, in combination:

signal generating means for producing a sinusoidal sampling referencesignal at a'frequency and amplitude always greater than the maximum an.-ticipated frequency and amplitude of an analog signal to be converted;reset means connected to receive the reference signal for producing areset pulse in each cycle thereof; andthreshold means including aplurality of threshold units each unit having subtracting means adaptedto receive the analog signal and connected to receive the sinusoidalreference signal for providing output difference signals indicative ofan amplitude difference between the analog and reference signals, andincluding first and second resistors having their one ends connected incommon and their other ends receiving respectively the analog andsinusoidal reference signals, 'and wherein the resistances of said firstand second resistors is selected to provide a greater peak current ofthe reference signal through said second resistor than theanticipatedpeak current of the analog signal through said first resistor, andsampling means connected to receive the difference signals and the resetpulse for producing parallel output signals indicative of a peakamplitude of respective ones of the difference signals between. adjacentreset pulses, and including a third resistor having its one endconnectedin common to said first and second resistors and its other endto a dc. signal, and a diode unit connected to an input to the one endsof said resistors and providing the threshold unit output signal, theduration between the reset pulses being preselected to include the timeof the peak amplitude of all anticipated frequencies of the differencesignals. 2. An analog-to-digital converter according to claim 1,wherein:

the resistance of said third resistor in respective ones of saidthreshold units is selected to provide a discrete biasing currentcorresponding to increasing increments of the signal difference betweenthe currents in said first and second resistors. 3. An analog-to-digitalconverter according to claim 2 further comprising:

said diode unit in respective ones of said threshold units including afirst tunnel diode connected at its anode to ground and connected at itscathode to the one ends of said first, second and third resistors forproviding a switching signal when the current sum of said first, secondand third resistor exceeds the switching current of said first tunneldiode, a blocking diode connected at its cathode to the cathode of saidfirst tunnel diode and at its anode to one end of a loading resistor, asecond tunnel diode connected at its cathode to the other end of saidloading resistor and at its anode to ground for storing the switching ofsaid first tunnel diode, and a reset resistor connected at one end tothe cathode of said second tunnel diode and the other end receiving thereset pulses for clearing the 4. A'high frequency analog-to-digitalconverter acsignal stored in said second tunn l diod a d f r cording toclaim3 further comprising, in combination: producing the output signalat the cathode of said encoder means F Y the p Output slgnals secondtunnel diode of respective ones of said for Producmgadlguany encodedslgnalthereofthresholdunits. 5 v

1. A high frequency analog-to-digital converter for an analog signalcomprising, in combination: signal generating means for producing asinusoidal sampling reference signal at a frequency and amplitude alwaysgreater than the maximum anticipated frequency and amplitude of ananalog signal to be converted; reset means connected to receive thereference signal for producing a reset pulse in each cycle thereof; andthreshold means including a plurality of threshold units each unithaving subtracting means adapted to receive the analog signaL andconnected to receive the sinusoidal reference signal for providingoutput difference signals indicative of an amplitude difference betweenthe analog and reference signals, and including first and secondresistors having their one ends connected in common and their other endsreceiving respectively the analog and sinusoidal reference signals, andwherein the resistances of said first and second resistors is selectedto provide a greater peak current of the reference signal through saidsecond resistor than the anticipated peak current of the analog signalthrough said first resistor, and sampling means connected to receive thedifference signals and the reset pulse for producing parallel outputsignals indicative of a peak amplitude of respective ones of thedifference signals between adjacent reset pulses, and including a thirdresistor having its one end connected in common to said first and secondresistors and its other end to a d.c. signal, and a diode unit connectedto an input to the one ends of said resistors and providing thethreshold unit output signal, the duration between the reset pulsesbeing preselected to include the time of the peak amplitude of allanticipated frequencies of the difference signals.
 2. Ananalog-to-digital converter according to claim 1, wherein: theresistance of said third resistor in respective ones of said thresholdunits is selected to provide a discrete biasing current corresponding toincreasing increments of the signal difference between the currents insaid first and second resistors.
 3. An analog-to-digital converteraccording to claim 2 further comprising: said diode unit in respectiveones of said threshold units including a first tunnel diode connected atits anode to ground and connected at its cathode to the one ends of saidfirst, second and third resistors for providing a switching signal whenthe current sum of said first, second and third resistor exceeds theswitching current of said first tunnel diode, a blocking diode connectedat its cathode to the cathode of said first tunnel diode and at itsanode to one end of a loading resistor, a second tunnel diode connectedat its cathode to the other end of said loading resistor and at itsanode to ground for storing the switching of said first tunnel diode,and a reset resistor connected at one end to the cathode of said secondtunnel diode and the other end receiving the reset pulses for clearingthe signal stored in said second tunnel diode and for producing theoutput signal at the cathode of said second tunnel diode of respectiveones of said threshold units.
 4. A high frequency analog-to-digitalconverter according to claim 3 further comprising, in combination:encoder means receiving the parallel output signals for producing adigitally encoded signal thereof.